The present invention relates to a semiconductor memory device, and more particularly to a read operation performed by the semiconductor memory device.
As a semiconductor memory device operates at a high frequency, it is more important for the semiconductor memory device to perform a read operation stably. Generally, the semiconductor memory device such as a double data rate (DDR) DRAM performs the read operation through a data output circuit. The data output circuit processes the data in synchronization with a clock signal outputted from a delay locked loop (DLL) circuit.
FIG. 1 is a block diagram illustrating a read path of a conventional DDR DRAM. The read path is provided with a clock buffer 10, a DLL circuit 20, a pulse generator 30, a pre driver 40, and a main driver 50.
The clock buffer 10 buffers an external clock ECLK, thereby generating an internal clock ICLK. The DLL circuit 20 performs a delay locking operation on the internal clock ICLK, thereby generating a rising clock RCLKDLL and a falling clock FCLKDLL. The pulse generator 30 generates pulse type signals through nodes A and B in response to the rising and falling clocks RCLKDLL and FCLKDLL, respectively. The pre driver 40 outputs data DATA0/DATA1 outputted from a pipe register, not shown, in synchronization with the pulse type signal. The main driver 50 outputs data DQ to external devices according to an output of the pre driver 40.
The read operation according to the read path in FIG. 1 is described below.
After the data DATA0/DATA1 are transmitted from the pipe register to the pre driver 40, an output timing of the data DATA0/DATA1 from the pre driver 40 is determined by the clocks outputted from the DLL circuit 20. That is, an even number of data DATA0 is outputted in response to the rising clock RCLKDLL and an odd number of data DATA1 is outputted in response to the falling clock FCLKDLL. In more detail, the data DATA0/DATA1 are outputted in response to the pulse type signal which is generated by the pulse generator 30 in response to the rising and falling clocks RCLKDLL and FCLKDLL.
The pulse generator 30 generates a pulse signal having a predetermined pulse width in order to transmit the data without fail. Accordingly, as the semiconductor memory device operates at a high frequency, the pulse width of the pulse signal becomes bigger than the half of that of the external clock. In that case, all of the transmission gates 402, 404, 406 and 408 in the pre driver 40 are open for a certain interval. At that time, if the data DATA0/DATA1 have different logic levels, i.e., logic high and low levels, respectively, there is a data fighting. At the data fighting, the output level of the pre driver 40 is pulled to one of two different data levels, depending on which has more driving ability. As a result, the data have different data eyes as described in FIG. 2.
FIG. 2 is a signal timing diagram illustrating the data eye according to the read path in FIG. 1. For example, the data fighting occurs when the even number of data DATA0 and the odd number of data DATA1 have logic high and low levels, respectively, and the enablement period of pulse signals on nodes A and B overlap with each other. If the logic low level has more driving ability than the logic high level, that is, a voltage supplying the logic low level has more power than the other, a data eye of the even number of data DATA0 decreases and a data eye of the odd number of data DATA1 increases. Accordingly, the semiconductor memory device cannot perform a data output operation stably and a malfunction is caused. In addition, current consumption increases by the data fighting.